BalCCon2k25

Join us as we explore Analog-to-Digital (ADC) and Digital-to-Analog (DAC) functionalities on the miniac FPGA platform. We'll detail the integration of these converters, adapting the Control and Status Registers (CSR) to support these new features and tuning the system for accurate signal reconstruction. A critical step involved achieving system-wide clock synchronization by operating the entire system at 65 [MHz] and implementing specific clock synchronization modules to eliminate signal jitter and stabilize high-speed data paths.

We will showcase two distinct data acquisition methods. First, the direct snooping approach, which involves reading individual ADC samples via UART. We'll discuss its inherent performance limitations due to PC-side latency. Second, we'll present our solution using RISC-V assisted snooping. This method leverages the on-FPGA RISC-V CPU to efficiently buffer samples in internal memory. By periodically reading these data blocks via UART, rather than individual samples, we significantly reduce transaction overhead, resulting in a much cleaner signal spectrum and demonstrating improved performance for real-time applications.

This presentation is ideal for hardware enthusiasts, embedded developers, and anyone interested in practical FPGA design and high-speed data acquisition. Basic knowledge of digital electronics, digital signal processing (DSP), and a curiosity about data acquisition systems will be beneficial. Attendees will gain insights into practical FPGA design challenges, performance optimization techniques, and the importance of hardware-software co-design.