BalCCon2k25

1. Introduction

We're going to start by giving you a compelling real-world example where high-speed, accurate signal acquisition is critical (e.g., medical diagnostics, industrial control, scientific research).
Then, we'll introduce the challenge: How do we acquire high-frequency analog signals reliably and efficiently using FPGAs, especially when we're interfacing with a PC? We'll highlight the common bottlenecks like communication overhead and latency.
Our goal for this talk: We're going to demonstrate two distinct approaches for signal acquisition on an FPGA platform (direct vs. RISC-V assisted snooping) and show you how we can overcome performance limitations for real-time applications.

Introducing the Miniac Platform:

We'll briefly introduce the Miniac FPGA platform, which is the hardware base for this work.
We'll mention its open-source nature and draw a parallel to similar projects, emphasizing its versatility for digital system designs.
We'll explain its relevance as a diagnostics tool and a versatile hardware base.

Core Hardware Integration & Synchronization:

We'll detail the process of integrating Analog-to-Digital (ADC) and Digital-to-Analog (DAC) converter modules onto the Miniac FPGA.
Control and Status Registers (CSR) Adaptation: We'll explain how we updated and extended existing CSRs to enable seamless software-hardware interaction for converter control and data exchange. We'll emphasize its importance for accurate signal reconstruction.

System-Wide Clock Synchronization:

We'll discuss the critical need for clock synchronization in high-speed data paths.
We'll explain our decision to operate the entire system at a single, shared clock frequency of 65 MHz (down from 80 MHz CPU, 65 MHz ADC, 125 MHz DAC).
We'll introduce how we used Input Double Data Rate (IDDR) and Output Double Data Rate (ODDR) modules, placed between ADC/CSR and CSR/DAC, to ensure correct data transfer and eliminate signal jitter.

1. Implemented Data Acquisition Methods

Direct Snooping Method (The Baseline - Why it's limited):
Concept: We'll describe this straightforward approach where individual ADC samples are read directly via UART to a PC.
Process Flow:
A signal is generated by a function generator.
It's sampled by the ADC.
The digitized samples are transmitted to the FPGA and written into a CSR.
Data from the CSR is then sent individually via UART to a PC.
A Python script on the PC continuously reads the data, calculates the sampling frequency, and plots the sampled/interpolated signal and frequency spectrum.

Limitations & Bottlenecks:

Primary Issue: We'll explain the significant overhead due to individual UART transactions for each ADC sample.
PC-side Latency: We'll discuss the compounding effect of operating system latencies, driver overhead, and Python library (PySerial) overhead.
Visual Aid: We'll show you the sampled signals and frequency spectrums, clearly demonstrating the limitations (e.g., 50 Hz, 100 Hz, 120 Hz sinusoids).

Indirect Snooping Method (The Solution - Leveraging RISC-V):

Concept: We'll introduce this batch-processing approach that leverages the on-FPGA RISC-V CPU to overcome the limitations of the direct method.
Process Flow:
The CPU on the FPGA continuously samples ADC data.
Samples are stored into an internal circular buffer (1024 32-bit samples).
UART communication to the PC is initiated only after the circular buffer is completely filled.
The entire content of the buffer is transmitted as a single block to the PC via UART.
A new Python script on the PC receives the complete data block.
The script processes the data: it plots raw sampled points, the interpolated signal, and performs a Fast Fourier Transform (FFT) for the frequency spectrum.
UART communication halts; the CPU resumes sampling to refill the buffer. The PC script waits for a pre-calculated duration before repeating.

Advantages & Performance Gains:

Reduced Transaction Overhead: We'll emphasize how batch processing significantly reduces communication overhead.
Improved Signal Spectrum: We'll explain how this leads to a much cleaner signal spectrum.
Demonstrated Performance: We'll showcase the substantial improvement for real-time applications.
Key Result: We'll highlight our ability to sample and reconstruct sine waves with frequencies up to approximately 250 kHz (a significant improvement over the 100 Hz limit of the direct method).
Visual Aid: We'll illustrate the successful sampling of higher frequency signals (e.g., 100 kHz, 200 kHz, 250 kHz sinusoids).

1. Experimental Results & Discussion

Comparative Analysis:
We'll directly compare the performance of the two methods, reiterating the limitations of the direct method (approx. 100 Hz effective sampling frequency due to UART overhead and PC-side latencies) versus the significant gains of the indirect method (up to 250 kHz).
We'll discuss the trade-offs: The direct method is conceptually simpler but practically limited; the indirect method is more complex due to CPU involvement but offers superior performance.
Key takeaway: We'll emphasize the critical advantages of FPGA-side buffering and batch processing for achieving significantly higher data throughput in similar embedded systems.
We'll emphasize our commitment to open science and community verification.

1. Conclusion
   A. Summary of Achievements:
   We'll recap our successful implementation and optimization of ADC/DAC features on the Miniac FPGA.
   We'll reiterate our core finding: The indirect, RISC-V assisted snooping method effectively overcomes low sampling frequency limitations of direct UART communication, enabling high-speed data acquisition.
   We'll emphasize the practical implications of this work for embedded systems and real-time applications.