This talk presents the integration of custom Verilog hardware IP blocks—including CORDIC, DAC, ADC, upsampler, and downsampler filters—within the LiteX SoC environment. It explains the complete hardware-software loop for controlling these blocks using LiteX-generated CSR registers accessible from a RISC-V CPU. We discuss how to create a LiteX target and platform file from scratch for a new FPGA board, bind CPU-accessible registers to Verilog module parameters, and automate the build and deployment process. Attendees will gain insights into debugging their designs with LiteScope, including practical challenges encountered when capturing signal waveforms over UART and Ethernet. The talk is geared toward FPGA engineers and embedded developers familiar with Verilog and SoC design who wish to expand their workflow to include automated integration and software-hardware co-design using LiteX.
Key Words ---- FPGA, LiteX, SoC, CPU, RISC-V, CSR
Introduction
First I would introduce the motivation for the project, focusing on building a flexible DSP pipeline in FPGA that can be controlled in real time. The key challenge addressed is the integration of custom Verilog IP blocks with a CPU in a way that enables runtime parameter updates as well as some troubles with using LiteX and pitfalls that can be avoided with clearer instructions. Some emphasis will also be on using the integrated Litescope ILA to debug the design in real time.
Hardware Architecture Overview
Briefly explain the hardware architecture of the system detailing the data flow from the ADC through downsamplers, CORDIC blocks, upsamplers, and the DAC. The interaction points of the LiteX SoC components, such as the RISC-V CPU and its control/status registers CSRs will be highlighted.
LiteX Integration and Platform Development
This subsection details the steps taken to create LiteX target and platform files for a custom FPGA board, including:
* Defining clocks, resets, and pin mappings.
* Automating the build, synthesis, and bitstream loading processes for a faster and configurable workflow with a Makefile
Binding CPU Registers to Verilog Modules
I would describe how CPU-accessible registers were created using LiteX’s CSRStorage, and how these registers were connected to inputs of Verilog module instances. This section includes code examples of binding the CORDIC phase increment register to generate sine or cosine waves with different frequencies.
Software Integration and Control
This part explains the development of software running on the RISC-V CPU, covering:
* Writing C programs to configure hardware blocks.
* Compiling these programs with the RISC-V toolchain.
* Uploading and executing binaries over UART to set runtime parameters.
Simulation in LiteX
LiteX’s built-in Verilator simulation can make it easy to test the SoC and DSP pipeline before deploying to hardware. By running the generated sim.py, you can verify register access, data flow, and CPU interaction entirely in software.
Debugging Using LiteScope
This subsection covers integrating LiteScope for signal observation and debugging:
* Adding signal taps to capture internal signals.
* Configuring LiteScope communication over UART and Ethernet.
* Issues encountered, such as slow UART performance for waveform capture, and solutions found using Ethernet.
Conclusion
I’ll wrap up by highlighting how LiteX made it much easier to bring together hardware and software in this project. Although the work is still ongoing, LiteX has already shown how valuable it is for quickly setting things up compared to building everything from scratch with pure RTL. Automating so many steps has freed up time to focus on actual design work instead of repetitive tasks. By the end of the talk, attendees will have a practical understanding of how to plug their own Verilog modules into a LiteX SoC, control them from a CPU, debug them with LiteScope, and streamline their workflow for faster development.
Project Links
You can check out the open-source FPGA projects mentioned in this paper at the following URLs:
My name is Tarik Hamedović, an electrical engineer from the University of Sarajevo, where I completed my Master’s at the Department of Automatic Control and Electronics.
My master’s thesis was building a software-defined radio (SDR) on FPGA using Python-based Amaranth, which is the upgraded version of Migen—the framework that LiteX itself is built on. I’ve been diving into FPGAs and open-source FPGA projects for more over a year now with Chili-chips.